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+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
ADDRESS [A7...A0]
00h
01h
Serial-Input Address Map
ACTIVE REGISTER
Output Control Register—OUTR
P o we r - S a ve C o n fig u r a tio n
Re gist e r —P S
D 7
OUT 8
D 6
OUT 7
D 5
OUT 6
D 4
OUT 5
D 3
OUT 4
D 2
OUT 3
D 1
OUT 2
D 0
OUT 1
MSB
LSB
Output Control Register—OUT R (Address = 00h)
Note: Setting D N to logic 1 turns on output OUT N+1 . Setting D N to logic 0, turns off OUT N+1 . Example: Setting D 2 = 1 turns on OUT 3 .
D 7
X
D 6
X
D 5
X
D 4
X
D 3
X
D 2
PS0
D 1
PS1
D 0
PS2
MSB
Power-Save Configuration Register—PS (Address= 01h)
LSB
PS0
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS2
0
1
0
1
0
1
0
1
POWER-SAVE CONFIGURATION
Power-save is disabled (Default Operation)
Power-save is enabled. V OUT set to 70% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 30%, typical after t PS ms.
Power-save is enabled. V OUT set to 60% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 40%, typical after t PS ms.
Power-save is enabled. V OUT set to 50% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 50%, typical after t PS ms.
Power-save is enabled. V OUT set to 40% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 60%, typical after t PS ms.
Power-save is enabled. V OUT set to 30% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 70%, typical after t PS ms.
Power-save is enabled. V OUT set to 20% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 80%, typical after t PS ms.
Power-save is enabled. V OUT set to 10% of V CC , typical after t PS ms (see Note 1), causes
I OUT _ to be reduced to approximately 90%, typical after t PS ms.
Power-Save Configuration Options
Note 1: The time period t PS is determined by the capacitor connected to PSAVE.
Figure 1. 16-Bit Register Map for MAX4822
When CS is low (MAX4822/MAX4823 device is select-
ed), data at DIN is clocked into the shift register syn-
chronously with SCLK’s rising edge. Driving CS from
low to high latches the data in the shift register (Figures
5 and 6).
DOUT is the output of the shift register. Data appears
on DOUT synchronously with SCLK’s falling edge and
is identical to the data at DIN delayed by eight clock
cycles for the MAX4823, or 16 clock cycles for the
MAX4822. When shifting the input data, A7 is the first
input bit in and out of the shift register for the MAX4822
device. D7 is the first bit in or out of the shift register for
10
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